There is an increasing demand for high voltage transistor devices capable of serving as an interface between low voltage transistors and high voltage end-use devices such as automotive components. It is highly desirable to manufacture high voltage transistors using similar process technology as used for low voltage transistors. The use of similar process technology minimizes the costs of producing high voltage transistors, and allows high and low voltage transistors to be manufactured as part of the same integrated circuit. However, conventional low voltage transistors, such as logic or memory transistors are designed for applications requiring high speed and low power consumption. Consequently, such transistors are highly susceptible to breakdown at sustained operating voltages of about 2 Volts or higher.
To allow operation at higher voltages one transistor design, known as a drain-extended transistor, one design incorporates a lightly to moderately doped region around one or both of heavily doped source and drain structures. This lightly to moderately doped region is known as a drain-extended well. Drain-extended transistors facilitate operation at high voltages (e.g., about 20 Volts or higher reverse bias applied to the drain) by directing a portion of the current from the source to drain to flow into the drain extended well.
Despite their improved performance, drain-extended transistors are still susceptible to high voltage breakdown at the edge of the silicon oxide isolation region, or moat, surrounding the source and drain structures. To reduce the occurrence of breakdown at the bird's beak edge at the moat perimeter, a racetrack or drain-centered layout, is used. In such a layout, the drain extension well surrounds the drain. Such drain-centered layouts, however, are still not entirely successful at avoiding high voltage breakdown. For instance, drain-extended transistors that have a racetrack layout continue to be susceptible to failure as a result of electrostatic discharge (ESD).
Accordingly, what is needed in the art is a method of manufacturing drain-extended transistors having reduced susceptibility to high voltage breakdown.